1. Field of Invention
The present invention relates to a memory device. More particularly, the present invention relates to a non-volatile memory and a manufacturing method and an erasing method thereof.
2. Description of Related Art
Memory, just as its name implies, is a semiconductor device for storing information and data. Memory is required to perform more and more effectively as the functions of microprocessors become stronger and the programs and calculations of software become larger. Memory with mass storage and low cost must be manufactured to meet the requirements of this trend. Therefore, the process of manufacturing such memory devices continuously develops for the semiconductor technology with higher integration.
Among memories, non-volatile memory is capable of storing, reading, or erasing data repeatedly, and the stored data will not disappear after the power supply is disconnected. Because of these advantages, non-volatile memory has become a memory device widely employed in personal computers and electronic apparatuses.
FIG. 1 is a schematic cross-sectional view of a conventional single poly non-volatile memory. The conventional single poly non-volatile memory consists of an N-type metal oxide semiconductor (NMOS) structure 10 and a P-type metal oxide semiconductor (PMOS) structure 12, and a field oxide layer 11 between the NMOS structure 10 and the PMOS 12 structure. The NMOS structure 10 is formed on a P-type substrate 14, and comprises a floating gate 16, a gate oxide layer 34, an N+ source doped region 18, and an N+ drain doped region 20. The PMOS structure 12 is formed on an N-type ion well region 22, and comprises a floating gate 24, a gate oxide layer 36, a P+ source doped region 26, and a P+ drain doped region 28. Additionally, an N-type channel barrier region 30 is disposed below the floating gate 24 and adjoins to one side of the P+ source doped region 26. Furthermore, a floating gate wire 32 should be disposed between the floating gates 16 and 24, in order to maintain the same potential for the floating gates 16 and 24.
However, the conventional single poly non-volatile memory encounters a few problems. For example, the conventional single poly non-volatile memory including the NMOS structure 10 and the PMOS structure 12 occupies a much larger chip area, which results in a relatively high production cost. On the other hand, the conventional single poly non-volatile memory takes a longer time to erase data, resulting in low operating speed of the memory device. Moreover, for the erasing operation of the conventional single poly non-volatile memory, the electrons are drawn from the floating gate to the substrate through the gate oxide layer, and the gate oxide layer may be easily damaged, thus adversely affecting the cycling number and the reliability of the memory device.
FIG. 2 is a schematic cross-sectional view of a split gate non-volatile memory. The conventional split gate non-volatile memory comprises a substrate 40, a floating gate 42, a control gate 44, a source region 46, and a drain region 48. However, the memory device employing the conventional split gate non-volatile memory has a larger size, and electron can be trapped easily for the erasing operation, thus lowering endurance of the memory device.